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this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. july 2014 docid022886 rev 6 1/46 1 VND7012AY-E double channel high-side driver with multisense analog feedback for automotive applications datasheet - preliminary data features ? general ? double channel smart high side driver with multisense analog feedback ? very low standby current ? compatible with 3 v and 5 v cmos outputs ? multisense diagnostic functions ? multiplexed analog feedback of: load current with high precision proportional current mirror, v cc supply voltage and t chip device temperature ? overload and short to ground (power limitation) indication ? thermal shutdown indication ? off-state open-load detection ? output short to v cc detection ? sense enable/ disable ? protections ? undervoltage shutdown ? overvoltage clamp ? load current limitation ? self limiting of fast thermal transients ? configurable latch-off on overtemperature or power limitation with dedicated fault reset pin ? loss of ground and loss of v cc ? reverse battery through self turn-on ? electrostatic discharge protection applications ? all types of automotive resistive, inductive and capacitive loads ? specially intended for automotive turn indicators (up to 3 x p27w or sae1156 and 2 x r5w paralleled or automotive headlamps) description the VND7012AY-E is a double channel high-side driver manufactured using st proprietary vipower ? m0-7 technology and housed in powersso-36 package. the device is designed to drive 12 v automotive grounded loads through a 3 v and 5 v cmos-compatible interface, providing protection and diagnostics. the device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. a faultrst pin unlatches the output in case of fault or disables the latch-off functionality. a dedicated multifunction multiplexed analog output pin delivers sophisticated diagnostic functions including high precision proportional load current sense, supply voltage feedback and chip temperature sense, in addition to the detection of overload and short circuit to ground, short to v cc and off-state open-load. a sense enable pin allows off-state diagnosis to be disabled during the module low-power mode as well as external sense resistor sharing among similar devices. max transient supply voltage v cc 41 v operating voltage range v cc 4 to 28 v typ. on-state resistance (per ch) r on 12 m current limitation (typ) i limh 75 a standby current (max) i stby 0.5 a *$3*&)7 powersso-36 www.st.com
contents VND7012AY-E 2/46 docid022886 rev 6 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 main electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1 power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3 current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4 negative voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1 gnd protection network against reverse battery . . . . . . . . . . . . . . . . . . . 27 4.2 immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . 28 4.3 mcu i/os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4 multisense - analog current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.4.1 principle of multisense signal generation . . . . . . . . . . . . . . . . . . . . . . . 31 4.4.2 t case and v cc monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4.3 short to vcc and off-state open-load detection . . . . . . . . . . . . . . . . . 34 4.5 maximum demagnetization energy (v cc = 16 v) . . . . . . . . . . . . . . . . . . . 35 5 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1 powersso-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.2 powersso-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.3 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
docid022886 rev 6 3/46 VND7012AY-E contents 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
list of tables VND7012AY-E 4/46 docid022886 rev 6 list of tables table 1. pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. switching (v cc =13v; -40c docid022886 rev 6 5/46 VND7012AY-E list of figures list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. i out /i sense vs. i out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5. current sense precision vs. i out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. switching times and pulse skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. multisense timings (current sense mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. multisense timings (chip temperature and vcc sense mode) . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. t dskon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 11. standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12. i gnd(on) vs. i out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13. logic input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14. logic input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 15. high level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 16. low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 17. logic input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 18. faultrst input clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 19. undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 20. on-state resistance vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 21. on-state resistance vs. v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 22. turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 23. turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 24. won vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 25. woff vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 26. i limh vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 27. off-state open-load voltage detection threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 28. v sense clamp vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 29. v senseh vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 30. application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 31. simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 32. multisense and diagnostic ? block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 33. multisense block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 34. analogue hsd ? open-load detection in off-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 35. open-load / short to vcc condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 36. gnd voltage shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 37. maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 38. powersso-36 pcb board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 39. r thj-amb vs pcb copper area in open box free air condition (one channel on) . . . . . . . . . . 37 figure 40. powersso-16 thermal impedance junction ambient single pulse (one channel on) . . . . . 38 figure 41. thermal fitting model of a double-channel hsd in powersso-16 . . . . . . . . . . . . . . . . . . 38 figure 42. powersso-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 43. powersso-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 44. powersso-36 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
block diagram and pin description VND7012AY-E 6/46 docid022886 rev 6 1 block diagram and pin description figure 1. block diagram table 1. pin functions name function v cc battery connection. output 0,1 power output. gnd ground connection. input 0,1 voltage controlled input pin with hysteresis, compatible with 3v and 5v cmos outputs. they control output switch state. multisense multiplexed analog sense output pin; delivers a current proportional to the selected diagnostic: load current, supply voltage or chip temperature. sen active high compatible with 3v and 5v cmos outputs; it enables the multisense diagnostic pin. sel 0,1 active high compatible with 3v and 5v cmos outputs; they address the multisense multiplexer. faultrst active low compatible with 3v and 5v cmos outputs; unlatches the output in case of fault; if kept low, sets the outputs in auto-restart mode. &kdqqho &rqwuro 'ldjqrvwlf &kdqqho 9 && 9 21 /lplwdwlrq &xuuhqw /lplwdwlrq 9 && 287 &odps ,qwhuqdovxsso\ &+ 287387 &+ 08; &xuuhqw 6hqvh *1' 8qghuyrowdjh vkxwgrzq 9 && *1' &odps )dxow 7 6kruwwr9 && 2shq/rdglq2)) 2yhuwhpshudwxuh 3rzhu/lplwdwlrq 7 9 6(16(+ ,1387 6(/ 6(/ 6(q 0xowlvhqvh )dxow567 ,1387 287387 9 && *dwh'ulyhu ("1($'5
docid022886 rev 6 7/46 VND7012AY-E block diagram and pin description figure 2. configuration diagram (top view) table 2. suggested connections for unused and not connected pins connection/pin multisense n.c. output input sen, selx, faultrst floating not allowed x (1) 1. x: do not care. xxx to ground through 1 k resistor x not allowed through 15 k resistor through 15 k resistor 287387 287387 287387 287387 3rzhu6623$&.$*( 287387 287387 6(/ 6(/ 1& ,1387 0xowl6hqvh *1' )dxow567 1& 1& ,1387 7$%9ff 287387 287387 6(q ("1($'5 1& 1& 1& 1& 1& 287387 287387 287387 287387 1& 1& 1& 1& 1& 1& 1& 1&
electrical specification VND7012AY-E 8/46 docid022886 rev 6 2 electrical specification figure 3. current and voltage conventions 2.1 absolute maximum ratings stressing the device above the rating listed in ta ble 3 may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to the conditions in table below for extended periods may affect device reliability. 6 ,1 287387 0xowl6hqvh )dxow567 6( q 6(/ ,1387 , ,1 , 6(/ , 6(q , )5 , *1' 9 6(16( 9 287 9 && 9 )q , 6 , 287 , 6(16( 9 && 9 6(/ 9 6(q 9 )5 *$3*&)7 note: v fn = v outn - v cc during reverse battery condition. table 3. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 38 v -v cc reverse dc supply voltage 16 v ccpk maximum transient supply voltage (iso7637-2:2004 pulse 5b level iv clamped to 40 v; r l =4 ) 40 v ccjs maximum jump start voltage for single pulse short circuit protection 28 -i gnd dc reverse ground pin current 200 ma i out output 0,1 dc output current internally limited a -i out reverse dc output current 22 i in input 0,1 dc input current -1 to 10 ma i sen sen dc input current i sel sel 0,1 dc input current i fr faultrst dc input current
docid022886 rev 6 9/46 VND7012AY-E electrical specification 2.2 thermal data v fr faultrst dc input voltage 7.5 v i sense multisense pin dc output current (v gnd =v cc and v sense <0v) 10 ma multisense pin dc output current in reverse (v cc < 0 v) -20 e max maximum switching energy (single pulse) (t demag =0.4ms; t jstart =150c) 144 mj v esd electrostatic discharge (jdec 22 a-114 f) ? input 0,1 ? multisense ? sen, sel 0,1 , faultrst ? output 0,1 ?v cc 4000 2000 4000 4000 4000 v v v v v v esd charge device model (cdm-aec-q100-011) 750 v t j junction operating temperature -40 to 150 c t stg storage temperature -55 to 150 table 3. absolute maximum ratings (continued) symbol parameter value unit table 4. thermal data symbol parameter typ. value unit r thj-board thermal resistance junction-board (jedec jesd 51-5 / 51-8) (1)(2) 1. one channel on. 2. device mounted on four-layers 2s2p pcb 4 c/w r thj-amb thermal resistance junction-ambient (jedec jesd 51-5) (1)(3) 3. device mounted on two-layers 2s0p pcb with 2 cm 2 heatsink copper trace 50.6 r thj-amb thermal resistance junction-ambient (jedec jesd 51-7) (1)(2) 16.6
electrical specification VND7012AY-E 10/46 docid022886 rev 6 2.3 main electrical characteristics 7v < v cc < 28 v; -40c < t j < 150c, unless otherwise specified. all typical values refer to v cc = 13 v; t j = 25c, unless otherwise specified. table 5. power section symbol parameter test conditions min. typ. max. unit v cc operating supply voltage 41328 v v usd undervoltage shutdown 4 v usdreset undervoltage shutdown reset 5 v usdhyst undervoltage shutdown hysteresis 0.3 r on on-state resistance (1) i out = 7 a; t j =25c 12 m i out = 7 a; t j = 150c 24 i out = 7 a; v cc =4v; t j =25c 18 r on_rev on-state resistance in reverse battery i out =-7a; v cc =-13v; t j = 25c 12 m v clamp clamp voltage i s =20ma; 25c docid022886 rev 6 11/46 VND7012AY-E electrical specification i l(off) off-state output current at v cc =13v (1) v in0,1 =v out0,1 =0v; v cc =13v; t j =25c 0 0.01 0.5 a v in0,1 =v out0,1 =0v; v cc =13v; t j =125c 03 v f output - v cc diode voltage (1) i out =-7a; t j = 150 c 0.7 v 1. for each channel. 2. powermos leakage included. 3. parameter specified by design; not subject to production test. table 6. switching (v cc = 13 v; -40 c < t j < 150 c, unless otherwise specified) (1) 1. see figure 6: switching times and pulse skew. symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time at t j =25c r l =1.84 10 50 120 s t d(off) turn-off delay time at t j =25c 10 45 100 (dv out /dt) on turn-on voltage slope at t j =25c r l =1.84 0.1 0.45 0.7 v/s (dv out /dt) off turn-off voltage slope at t j = 25 c 0.2 0.5 0.8 w on switching energy losses at turn-on (t won ) r l =1.84 ?0.61.4 (2) 2. parameter guaranteed by design and characterization, not subject to production test. mj w off switching energy losses at turn-off (t woff ) r l =1.84 ?0.61.3 (2) mj t skew differential pulse skew (t phl - t plh ) see figure 6 r l =1.84 -60 -10 40 s table 7. logic inputs (7 v < v cc < 28 v; -40c < t j <150c) symbol parameter test conditions min. typ. max. unit input 0,1 characteristics v il input low level voltage 0.9 v i il low level input current v in =0.9v 1 a v ih input high level voltage 2.1 v i ih high level input current v in =2.1v 10 a v i(hyst) input hysteresis voltage 0.2 v v icl input clamp voltage i in =1ma 5.3 7.2 v i in =-1ma -0.7 faultrst characteristics v frl input low level voltage 0.9 v table 5. power section symbol parameter test conditions min. typ. max. unit
electrical specification VND7012AY-E 12/46 docid022886 rev 6 i frl low level input current v in =0.9v 1 a v frh input high level voltage 2.1 v i frh high level input current v in =2.1v 10 a v fr(hyst) input hysteresis voltage 0.2 v v frcl input clamp voltage i in =1ma 5.3 7.5 v i in =-1ma -0.7 sel 0,1 characteristics (7 v < v cc <18v) v sell input low level voltage 0.9 v i sell low level input current v in =0.9v 1 a v selh input high level voltage 2.1 v i selh high level input current v in =2.1v 10 a v sel(hyst) input hysteresis voltage 0.2 v v selcl input clamp voltage i in =1ma 5.3 7.2 v i in =-1ma -0.7 sen characteristics (7 v < v cc <18v) v senl input low level voltage 0.9 v i senl low level input current v in =0.9v 1 a v senh input high level voltage 2.1 v i senh high level input current v in =2.1v 10 a v sen(hyst) input hysteresis voltage 0.2 v v sencl input clamp voltage i in =1ma 5.3 7.2 v i in =-1ma -0.7 table 8. protections (7 v < v cc <18v; -40c docid022886 rev 6 13/46 VND7012AY-E electrical specification t j_sd dynamic temperature 60 k t latch_rst fault reset time for output unlatch (2) v fr = 5 v to 0 v; v sen =5v; v in0,1 =5v; v sel0,1 =0v 31020s v demag turn-off output voltage clamp i out =2a; l=6mh; t j =-40c v cc -38 v i out =2a; l=6mh; t j = 25c to 150c v cc -41 v cc -46 v cc -52 v on output voltage drop limitation i out =0.7a 20 mv 1. parameter guaranteed by an indirect test sequence. 2. parameter guaranteed by design and characterization; not subject to production test. table 9. multisense (7 v < v cc < 18 v; -40c < t j < 150c) symbol parameter test conditions min. typ. max. unit v sense_cl multisense clamp voltage v sen =0v; i sense =1ma -17 -12 v v sen =0v; i sense =-1ma 7 v current sense characteristics k ol i out /i sense i out = 10 ma; v sense = 0.5 v; v sen =5v 1400 dk cal /k cal (1)(2) current sense ratio drift at calibration point i cal =130ma; i out = 10 ma to 250 ma; v sense = 0.5 v; v sen =5v -35 35 % k led i out /i sense i out =250ma; v sense = 0.5 v; v sen =5v 2490 5100 8000 k 0 i out /i sense i out =0.7a; v sense = 0.5 v; v sen =5v 2560 5120 7680 dk 0 /k 0 (1)(2) current sense ratio drift i out =0.7a; v sense = 0.5 v; v sen =5v -25 25 % k 1 i out /i sense i out =1.4a; v sense =4v; v sen =5v 3480 4900 6470 dk 1 /k 1 (1)(2) current sense ratio drift i out =1.4a; v sense =4v; v sen =5v -20 20 % k 2 i out /i sense i out = 7 a; v sense =4v; v sen =5v 3410 4280 5120 dk 2 /k 2 (1)(2) current sense ratio drift i out = 7 a; v sense =4v; v sen =5v -10 10 % k 3 i out /i sense i out =21a; v sense =4v; v sen =5v 3810 4300 4660 dk 3 /k 3 (1)(2) current sense ratio drift i out =21a; v sense =4v; v sen =5v -5 5 % table 8. protections (7 v < v cc < 18 v; -40c < t j < 150c) (continued) symbol parameter test conditions min. typ. max. unit
electrical specification VND7012AY-E 14/46 docid022886 rev 6 i sense 0 multisense leakage current multisense disabled: v sen =0v; 00.5a multisense disabled: -1 v < v sense <5v (1) -0.5 0.5 a multisense enabled: v sen =5v; all channel on; i outx = 0 a; ch x diagnostic selected; ? e.g. ch 0 : v in0 =5v; v in1 =5v; v sel0 =0v; v sel1 =0v; i out0 = 0 a; i out1 =7a 02a multisense enabled: v sen =5v; ch x channel off; ch x diagnostic selected; ? e.g. ch 0 : v in0 =0v; v in1 =5v; v sel0 =0v; v sel1 =0v; i out1 =7a 02a v out_msd (1) output voltage for multisense shutdown v sen =5v; r sense =2.7k ? e.g. ch 0 : v in0 =5v; v sel0 =0v; v sel1 =0v; i out0 =7a 5v v sense_sat multisense saturation voltage v cc =7v; r sense =2.7k; v sen =5v; v in0 =5v; v sel0,1 =0v; i out0 =21a; t j = 150c 5v i sense_sat (1) cs saturation current v cc =7v; v sense =4v; v sen =5v; v in0 =5v; v sel0,1 =0v; t j = 150c 4ma i out_sat (1) output saturation current v cc =7v; v sense =4v; v in0 =5v; v sen =5v; v sel0,1 =0v; t j = 150c 23 a off-state diagnostic v ol off-state open-load voltage detection threshold v sen =5v; ch x off; ch x diagnostic selected ? e.g: ch 0 v in0 =0v; v sel0 =0v; v sel1 =0v; 234v i l(off2) off state output sink current v in =0v; v out =v ol ; t j = -40c to 125c -100 -15 a table 9. multisense (7 v < v cc < 18 v; -40c < t j < 150c) (continued) symbol parameter test conditions min. typ. max. unit
docid022886 rev 6 15/46 VND7012AY-E electrical specification t dstkon off-state diagnostic delay time from falling edge of input (see xxx) v sen =5v; ch x on to off transition ch x diagnostic selected ? e.g: ch 0 v in0 = 5 v to 0 v; v sel0 =0v; v sel1 =0v; i out0 = 0 a; v out =4v 100 350 700 s t d_ol_v settling time for valid off-state open load diagnostic indication from rising edge of sen v in0 =0v; v in1 =0v; v fr =0v; v sel0 =0v; v sel1 =0v; v out0 =4v; v sen = 0 v to 5 v 60 s t d_vol off-state diagnostic delay time from rising edge of v out v sen =5v; ch x off ch x diagnostic selected ? e.g: ch 0 v in0 =0v; v sel0 =0v; v sel1 =0v; v out =0vto4v 530s chip temperature analog feedback v sense_tc multisense output voltage proportional to chip temperature v sen =5v; v sel0 =0v; v sel1 =5v; v in0,1 =0v; r sense =1k ; t j =-40c 2.325 2.41 2.495 v v sen =5v; v sel0 =0v; v sel1 =5v; v in0,1 =0v; r sense =1k ; t j =25c 1.985 2.07 2.155 v v sen =5v; v sel0 =0v; v sel1 =5v; v in0,1 =0v; r sense =1k ; t j =125c 1.435 1.52 1.605 v dv sense_tc /dt (1) temperature coefficient t j = -40c to 150c -5.5 mv/k transfer function v sense_tc (t) = v sense_tc (t 0 )+dv sense_tc /dt*(t- t 0 ) v cc supply voltage analog feedback v sense_vcc multisense output voltage proportional to v cc supply voltage v cc =13v; v sen =5v; v sel0 =5v; v sel1 =5v; v in0,1 =0v; r sense =1k 3.16 3.23 3.3 v transfer function (3) v sense_vcc =v cc /4 fault diagnostic feedback (see table 10 ) v senseh multisense output voltage in fault condition v cc =13v; r sense =1k ? e.g: ch 0 in open load v in0 =0v; v sen =5v; v sel0 =0v; v sel1 =0v; i out0 = 0 a; v out =4v 56.6v table 9. multisense (7 v < v cc < 18 v; -40c < t j < 150c) (continued) symbol parameter test conditions min. typ. max. unit
electrical specification VND7012AY-E 16/46 docid022886 rev 6 i senseh multisense output current in fault condition v cc =13v; v sense = 5 v 7 20 30 ma multisense timings (current sense mode - see figure 7 ) (4) t dsense1h current sense settling time from rising edge of sen v in =5v; v sen =0vto5v; r sense =1k ; r l =1.84 60 s t dsense1l current sense disable delay time from falling edge of sen v in =5v; v sen =5vto0v; r sense =1k ; r l =1.84 520s t dsense2h current sense settling time from rising edge of input v in = 0 v to 5 v; v sen =5v; r sense =1k ; r l =1.84 100 250 s t dsense2h current sense settling time from rising edge of i out (dynamic response to a step change of i out ) v in =5v; v sen =5v; r sense =1k ; r l =1.84 100 s t dsense2l current sense turn- off delay time from falling edge of input v in = 5 v to 0 v; v sen =5v; r sense =1k ; r l =1.84 50 250 s multisense timings (chip temperature sense mode - see figure 8 ) (4) t dsense3h v sense_tc settling time from rising edge of sen v sen = 0 v to 5 v; v sel0 =0v; v sel1 =5v; r sense =1k 60 s t dsense3l v sense_tc disable delay time from falling edge of sen v sen = 5 v to 0 v; v sel0 =0v; v sel1 =5v; r sense =1k 20 s multisense timings (v cc voltage sense mode - see figure 8 ) (4) t dsense4h v sense_vcc settling time from rising edge of sen v sen = 0 v to 5 v; v sel0 =5v; v sel1 =5v; r sense =1k 60 s t dsense4l v sense_vcc disable delay time from falling edge of sen v sen = 5 v to 0 v; v sel0 =5v; v sel1 =5v; r sense =1k 20 s multisense timings (multiplexer transition times) (4) t d_xtoy multisense transition delay from ch x to ch y v in0 =5v; v in1 =5v; v sen =5v; v sel1 =0v; v sel0 =0vto5v; i out0 = 0a; i out1 = 3 a; r sense =1k 20 s table 9. multisense (7 v < v cc < 18 v; -40c < t j < 150c) (continued) symbol parameter test conditions min. typ. max. unit
docid022886 rev 6 17/46 VND7012AY-E electrical specification t d_cstotc multisense transition delay from current sense to t c sense v in0 =5v; v sen =5v; v sel0 =0v; v sel1 =0vto5v; i out0 = 3.5 a; r sense =1k 60 s t d_tctocs multisense transition delay from t c sense to current sense v in0 =5v; v sen =5v; v sel0 =0v; v sel1 =5vto0v; i out0 = 3.5 a; r sense =1k 20 s t d_cstovcc multisense transition delay from current sense to v cc sense v in1 =5v; v sen =5v; v sel0 =5v; v sel1 =0vto5v; i out1 = 3.5a; r sense =1k 60 s t d_vcctocs multisense transition delay from v cc sense to current sense v in1 =5v; v sen =5v; v sel0 =5v; v sel1 =5vto0v; i out1 = 3.5 a; r sense =1k 20 s t d_tctovcc multisense transition delay from t c sense to v cc sense v cc =13v; t j =125c; v sen =5v; v sel0 =0vto5v; v sel1 =5v; r sense =1k 20 s t d_vcctotc multisense transition delay from v cc sense to t c sense v cc =13v; t j =125c; v sen =5v; v sel0 =5vto0v; v sel1 =5v; r sense =1k 20 s t d_cstovsenseh multisense transition delay from stable current sense on ch x to v senseh on ch y v in0 =5v; v in1 =0v; v sen =5v; v sel1 =0v; v sel0 =0vto5v; i out0 = 7 a; v out1 =4v; r sense =1k 20 s 1. parameter specified by design; not subject to production test. 2. all values refer to v cc =13v; t j = 25 c, unless otherwise specified. 3. v cc sensing and t c sensing are referred to gnd potential. 4. transition delay are measured up to +/- 10% of final conditions. table 9. multisense (7 v < v cc < 18 v; -40c < t j < 150c) (continued) symbol parameter test conditions min. typ. max. unit
electrical specification VND7012AY-E 18/46 docid022886 rev 6 figure 4. i out /i sense vs. i out figure 5. current sense precision vs. i out ("1($'5 ? ? e ? ? ? ? e ? ?e?????e docid022886 rev 6 19/46 VND7012AY-E electrical specification figure 6. switching times and pulse skew figure 7. multisense timings (current sense mode) 9287 w 9ff wzrq 9ff 9ff wzrii ,1387 wgrq ws/+ ws+/ wgrii w g9 287 gw 21 2)) g9 287 gw ("1($'5 &855(176(16( ,1 6(q , 287 w '6(16(+ w '6(16(/ w '6(16(/ w '6(16(+ 6(/ 6(/ /rz +ljk /rz +ljk /rz +ljk ("1($'5
electrical specification VND7012AY-E 20/46 docid022886 rev 6 figure 8. multisense timings (chip temperature and v cc sense mode) figure 9. t dskon 6(16( 6(q 9 && w '6(16(+ w '6(16(/ w '6(16(/ w '6(16(+ 6(/ 6(/ /rz +ljk /rz +ljk /rz +ljk 9 6(16( 9 6(16(b9&& 9 6(16( 9 6(16(b7& 9&&92/7$*(6(16(02'( &+,37(03(5$785(6(16(02'( ("1($'5 7 '67.21 9 ,1387 9 287 0xowl6hqvh 9 287 !9 2/ *$3*&)7
docid022886 rev 6 21/46 VND7012AY-E electrical specification table 10. truth table mode conditions in x fr sen sel x out x multisense comments standby all logic inputs low l l l l l hi-z low quiescent current consumption normal nominal load connected; t j <150c lx refer to table 11 l refer to table 11 hl h outputs configured for auto-restart hh h outputs configured for latch off overload overload or short to gnd causing: t j >t tsd or t j > t j_sd lx refer to table 11 l refer to table 11 hl h output cycles with temperature hysteresis h h l output latches off under- voltage v cc v usd + v usdhyst (rising) off-state diagnostics short to v cc lx refer to table 11 h refer to table 11 open-load l x h external pull up negative output voltage inductive loads turn-off lx refer to table 11 <0v refer to table 11 table 11. multisense multiplexer addressing sen sel 1 sel 0 muxchannel multisense output normal mode overload off-state diag. (1) 1. in case the output channel corresponding to the selected mux channel is latched off while the relevant input is low, multisense pin delivers feedback according to off-state diagnostic. example 1: fr = 1; in 0 = 0; out 0 = l (latched); mux channel = channel 0 diagnostic; mutisense = 0 example 2: fr = 1; in 0 = 0; out 0 = latched, v out0 >v ol ; mux channel = channel 0 diagnostic; mutisense = v senseh negative output lxx hi-z hll channel 0 diagnostic i sense = 1/k * i out0 v sense = v senseh v sense = v senseh hi-z hlh channel 1 diagnostic i sense = 1/k * i out1 v sense = v senseh v sense = v senseh hi-z hhlt chip sense v sense =v sense_tc hhhv cc sense v sense =v sense_vcc
electrical specification VND7012AY-E 22/46 docid022886 rev 6 2.4 electrical characteristics curves figure 10. off-state output current figure 11. standby current figure 12. i gnd(on) vs. i out figure 13. logic input high level voltage figure 14. logic input low level voltage figure 15. high level logic input current ("1($'5 7>?&@ ,orii>q$@ 2ii6wdwh 9ff 9 9lq 9rxw ("1($'5 7>?&@ ,67%<>?$@ 9ff 9 ("1($'5 7>?&@ ,*1'21>p$@ 9ff 9 ,rxw ,rxw $ ("1($'5 7>?&@ 9l+9)5+96(/+96(q+>9@ ("1($'5 7>?&@ 9lo/9)5/96(//96(q/>9@ ("1($'5 7>?&@ ,l+,)5+,6(/+,6(q+>?$@
docid022886 rev 6 23/46 VND7012AY-E electrical specification figure 16. low level logic input current figure 17. logic input hysteresis voltage figure 18. faultrst input clamp voltage figure 19. undervoltage shutdown figure 20. on-state resistance vs. t case figure 21. on-state resistance vs. v cc ("1($'5 7>?&@ ,l/,)5/,6(//,6(q/>?$@ ("1($'5 7>?&@ 9lk\vw9)5k\vw96(/k\vw96(qk\vw>9@ ("1($'5 7>?&@ 9)5&/>9@ ,lq p$ ,lq p$ ("1($'5 7>?&@ 986'>9@ ("1($'5 7>?&@ 5rq>p2kp@ ,rxw $ 9ff 9 ("1($'5 9ff>9@ 5rq>p2kp@ 7 ?& 7 ?& 7 ?& 7 ?&
electrical specification VND7012AY-E 24/46 docid022886 rev 6 figure 22. turn-on voltage slope figure 23. turn-off voltage slope figure 24. won vs. t case figure 25. woff vs. t case figure 26. i limh vs. t case figure 27. off-state open-load voltage detection threshold ("1($'5 7>?&@ g9rxwgw2q>9?v@ 9ff 9 5o ("1($'5 7>?&@ g9rxwgw2ii>9?v@ 9ff 9 5o ("1($'5 7>?&@ :rq>p-@ ("1($'5 7>?&@ :rii>p-@ ("1($'5 7>?&@ ,olpk>$@ 9ff 9 ("1($'5 7>?&@ 92/>9@
docid022886 rev 6 25/46 VND7012AY-E electrical specification figure 28. v sense clamp vs. t case figure 29. v senseh vs. t case ("1($'5 7>?&@ 96(16(b&/>9@ ,lq p$ ,lq p$ ("1($'5 7>?&@ 96(16(+>9@
protections VND7012AY-E 26/46 docid022886 rev 6 3 protections 3.1 power limitation the basic working principle of this protection consists of an indirect measurement of the junction temperature swing t j through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output mosfet as soon as t j exceeds the safety level of t j_sd . according to the voltage level on the faultrst pin, the output mosfet switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (faultrst = low) or remains off (faultrst = high). the protection prevents fast thermal transient effects and, consequently, reduces thermo-mechanical fatigue. 3.2 thermal shutdown in case the junction temperature of the device exceeds the maximum allowed threshold (typically 175c), it automatically switches off and the diagnostic indication is triggered. according to the voltage level on the faultrst pin, the device switches on again as soon as its junction temperature drops to t r (see ta ble 8 , faultrst = low) or remains off (faultrst = high). 3.3 current limitation the device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, i limh , by operating the output power mosfet in the active region. 3.4 negative voltage clamp in case the device drives inductive load, the output voltage reaches negative value during turn off. a negative voltage clamp structure limits the maximum negative voltage to a certain value, v demag (see tab le 8 ), allowing the inductor energy to be dissipated without damaging the device.
docid022886 rev 6 27/46 VND7012AY-E application information 4 application information figure 30. application diagram 4.1 gnd protection network against reverse battery figure 31. simplified internal structure 9 '' 287 287 287 287 $'&lq *1' 5surw 5surw 5surw 5surw 5vhqvh 5surw &h[w 287 9 /rjlf 287 *1' )5 ,1387 6(q 6(/ 9 && &6 &xuuhqwpluuru 'og ("1($'5 0&8 ,1387 6(q 0xowlvhqvh )dxow567 9ff 287387 *1' 5surw 5surw 5surw 5surw 'og 5vhqvh 9 *1' ("1($'5
application information VND7012AY-E 28/46 docid022886 rev 6 the device does not need any external components to protect the internal logic in case of a reverse battery condition. the protection is provided by internal structures. in addition, due to the fact that the output mosfet turns on even in reverse battery mode, thus providing the same low ohmic path as in regular operating conditions, no additional power dissipation has to be considered. 4.2 immunity against transient electrical disturbances the immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the v cc pin, is tested in accordance with iso7637-2:2011 (e) and iso 16750-2:2010. the related function performance status classification is shown in tab le 12 . test pulses are applied directly to dut (device under test) both in on and off-state and in accordance to iso 7637-2:2011(e), chapter 4. the dut is intended as the present device only, without components and accessed through v cc and gnd terminals. status ii is defined in iso 7637-1 function performance status classification (fpsc) as follows: ?the function does not perform as designed during the test but returns automatically to normal operation after the test?. 4.3 mcu i/os protection if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line both to prevent the microcontroller i/o pins to latch-up and to protect the hsd inputs. table 12. iso 7637-2 - electrical transient conduction along supply line test pulse 2011(e) test pulse severity level with status ii functional performance status minimum number of pulses or test time burst cycle / pulse repetition time pulse duration and pulse generator internal impedance level u s (1) 1. u s is the peak amplitude as defined for each test pulse in iso 7637-2:2011(e), chapter 5.6. min max 1 iii -112v 500 pulses 0,5 s 2ms, 10 2a iii +55v 500 pulses 0,2 s 5 s 50 s, 2 3a iv -220v 1h 90 ms 100 ms 0.1 s, 50 3b iv +150v 1h 90 ms 100 ms 0.1 s, 50 4 (2) 2. test pulse from iso 7637-2:2004(e). iv -7v 1 pulse 100ms, 0.01 load dump according to iso 16750-2:2010 te st b (3) 3. with 40 v external suppressor referred to ground (-40c < t j < 150c). 40v 5 pulse 1 min 400ms, 2
docid022886 rev 6 29/46 VND7012AY-E application information the value of these resistors is a compromise between the leakage current of microcontroller and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of microcontroller i/os. equation 1 v ccpeak /i latchup r prot (v oh c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = -150 v; i latchup 20ma; v oh c 4.5v 7.5 k r prot 140 k . recommended values: r prot =15k 4.4 multisense - analog current sense diagnostic information on device and load status are provided by an analog output pin (multisense) delivering the following signals: ? current monitor: current mirror of channel output current ? v cc monitor: voltage propotional to v cc ? t case : voltage propotional to chip temperature those signals are routed through an analog multiplexer which is configured and controlled by means of selx and sen pins, according to the address map in table 11 .
application information VND7012AY-E 30/46 docid022886 rev 6 figure 32. multisense and diagnostic ? block diagram 6(/ 6(q 0xowl6hqvh 5 6(16( 5 3527 7rx&$'& 287 &xuuhqw 6hqvh )dxow )dxow 'ldjqrvwlf 9 6(16(+ 08; 7hps 9 && , 6(16( , 287 .idfwru 9 && 021,725 7(03 021,725 &855(17 021,725 *dwh'ulyhu 9&&287 &odps 7 9&&*1' &odps ,qwhuqdo6xsso\ 8qghuyrowdjh vkxwgrzq 921 /lplwdwlrq &xuuhqw /lplwdwlrq 3rzhu/lplwdwlrq 2yhuwhpshudwxuh 6kruwwr9&& 2shq/rdglq2)) 6(/ &rqwuro 'ldjqrvwlf *1' 9&& ,1387 )dxow567 5hyhuvh %dwwhu\ ("1($'5
docid022886 rev 6 31/46 VND7012AY-E application information 4.4.1 principle of multisense signal generation figure 33. multisense block diagram current monitor when current mode is selected in the multisense, this output is capable to provide: ? current mirror proportional to the load current in normal operation , delivering current proportional to the load according to known ratio named k ? diagnostics flag in fault conditions delivering fixed voltage v senseh the current delivered by the current sense circuit, i sense , can be easily converted to a voltage v sense by using an external sense resistor, r sense , allowing continuous load monitoring and abnormal condition detection. normal operation (channel on, no fault, sen active) while device is operating in normal conditions (no fault intervention), v sense calculation can be done using simple equations current provided by multisense output: i sense = i out /k ).054 9ff 287 7rx&$'& 5 3527 5 6(16( 0dlq026 6hqvh026 9edw0rqlwru 7hpshudwxuhprqlwru )dxow 08/7,6(16( 0xowlvhqvh6zlwfk%orfn &xuuhqwvhqvh *$3*&)7
application information VND7012AY-E 32/46 docid022886 rev 6 voltage on r sense : v sense = r sense . i sense = r sense . i out /k where : ? v sense is voltage measurable on r sense resistor ? i sense is current provided from multisense pin in current output mode ? i out is current flowing through output ? k factor represents the ratio between powermos cells and sensemos cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying ratio between i out and i sense . failure flag indication in case of power limitation/overtemperature, the fault is indicated by the multisense pin which is switched to a ?current limited? voltage source, v senseh (see table 9 ). in any case, the current sourced by the multisense in this condition is limited to i senseh (see table 9 ). figure 34. analogue hsd ? open-load detection in off-state n n n n n 9 9edw 5vhqvh n 9 '' 287 287 287 287 $'&lq *1' 287 q) *1' *1' *1' *1' *1' *1' q)9 q) q)9 *1' 0lfurfrqwuroohu 287387 9edw n ([whuqdo 3xoo8s vzlwfk /rjlf 287 *1' )5 ,1387 6(q 6(/ 9 && &6 &xuuhqwpluuru ("1($'5
docid022886 rev 6 33/46 VND7012AY-E application information figure 35. open-load / short to v cc condition 4.4.2 t case and v cc monitor in this case, multisense output operates in voltage mode and output level is referred to device gnd. care must be taken in case a gnd network protection is used, because of a voltage shift is generated between device gnd and the microcontroller input gnd reference. figure 36 shows link between v measured and real v sense signal. table 13. multisense pin levels in off-state condition output multisense sen open-load v out >v ol hi-z l v senseh h v out v ol hi-z l v senseh h nominal v out application information VND7012AY-E 34/46 docid022886 rev 6 figure 36. gnd voltage shift v cc monitor battery monitoring channel provides v sense = v cc / 4. case temperature monitor case temperature monitor is capable to provide information about the actual device temperature. since a diode is used for temperature sensing, the following equation describes the link between temperature and output v sense level: v sense_tc (t) = v sense_tc (t 0 )+dv sense_tc /dt*(t-t 0 ) where dv sense_tc / dt ~ typically -5.5 mv/k (for temperature range (-40 c to 150 c). 4.4.3 short to v cc and off-state open-load detection short to v cc a short circuit between v cc and output is indicated by the relevant current sense pin set to v senseh during the device off-state. small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit. off-state open-load with external circuitry detection of an open-load in off mode requires an external pull-up resistor r pu connecting the output to a positive supply voltage v pu . it is preferable v pu to be switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. 7rx&$'& 9 6(16( 9 3527 0xowlvhqvhyrowdjhprgh 9 6(16(+ 9 && prqlwru 7 &$6( prqlwru *1' 6(q 6(/ 287 9 && 0xowlvhqvh 6(/ ,1 )dxow567 5 3527 n ' *1' 5 6(16( 9 0($685(' 5 3527 9 %$7 q)9 '!0'#&4
docid022886 rev 6 35/46 VND7012AY-E application information r pu must be selected in order to ensure v out > v olmax in accordance with the following equation: equation 2 4.5 maximum demagnetization energy (v cc =16v) figure 37. maximum turn off current versus inductance 1. values are generated with r l =0 . in case of repetitive pulses, t jstart (at the beginning of each demagnetization) of every pulse must not exceed the temperature specif ied above for curves a and b. r pu v pu 4 ? i loff2 () min @ 4v ----------------------------------------- < ,$ /p+ 91'$< 0d[lpxpwxuqriifxuuhqwyhuvxvlqgxfwdqfh 91'$<6lqjoh3xovh 5hshwlwlyhsxovh7mvwduw ?& 5hshwlwlyhsxovh7mvwduw ?& ("1($'5
package and pcb thermal data VND7012AY-E 36/46 docid022886 rev 6 5 package and pcb thermal data 5.1 powersso-36 thermal data figure 38. powersso-36 pcb board ("1($'5
docid022886 rev 6 37/46 VND7012AY-E package and pcb thermal data figure 39. r thj-amb vs pcb copper area in open box free air condition (one channel on) table 14. pcb properties dimension value board finish thickness 1.6 mm +/- 10% board dimension 129 mm x 86 mm board material fr4 cu thickness (outer layers) 0.070 mm cu thickness (inner layers) 0.035 mm thermal via separation 1.2 mm thermal via diameter 0.3 mm +/- 0.08 mm cu thickness on vias 0.025 mm footprint dimension 4.1 mm x 6.5 mm 57+mdpe 35)k@bnc ?$8
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package and pcb thermal data VND7012AY-E 38/46 docid022886 rev 6 figure 40. powersso-16 thermal impedance junction ambient single pulse (one channel on) equation 3: pulse calculation formula where = t p /t figure 41. thermal fitting model of a double-channel hsd in powersso-16 1. the fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cyc ling during thermal shutdown) are not triggered. =7+ &: 7lphv &x fp &x fp &x irrwsulqw /d\hu ("1($'5 z th r th z thtp 1 ? () + ? = ("1($'5
docid022886 rev 6 39/46 VND7012AY-E package and pcb thermal data table 15. thermal parameters area/island (cm 2 ) footprint 2 8 4l r1 = r7 (c/w) 0.2 r2 = r8 (c/w) 1 r3 (c/w) 3.4 3.4 3.4 2.4 r4 (c/w) 8 664 r5 (c/w) 20 14 10 2 r6 (c/w) 30 26 15 7 c1 = c7 (w.s/c) 0.0025 c2 = c8 (w.s/c) 0.01 c3 (w.s/c) 0.1 0.1 0.1 0.8 c4 (w.s/c) 0.5 0.8 0.8 0.8 c5 (w.s/c) 1 2 3 10 c6 (w.s/c) 3 5 9 18
package information VND7012AY-E 40/46 docid022886 rev 6 6 package information 6.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at www.st.com . ecopack ? is an st trademark. 6.2 powersso-36 mechanical data figure 42. powersso-36 package dimensions
docid022886 rev 6 41/46 VND7012AY-E package information l table 16. powersso-36 mechanical data symbol millimeters min typ max a 2.15 - 2.45 a2 2.15 - 2.35 a1 0 - 0.1 b 0.18 - 0.36 c 0.23 - 0.32 d 10.10 - 10.50 e 7.4 - 7.6 e-0.5- e3 - 8.5 - f-2.3- g- -0.1 h 10.1 - 10.5 h- -0.4 k0-8 l 0.55 - 0.85 m-4.3- n- -10 o-1.2 q-0.8- s-2.9- t-3.65- u-1.0- x (1) 1. corresponding to internal variation c. 4.3 - 5.2 y (1) 6.9 - 7.5
package information VND7012AY-E 42/46 docid022886 rev 6 6.3 packing information figure 43. powersso-36 tube shipment (no suffix) figure 44. powersso-36 tape and reel shipment (suffix ?tr?) a c b all dimensions are in mm. base q.ty 49 bulk q.ty 1225 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6 base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 100 t (max) 30.4 reel dimensions tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d ( 0.05) 1.55 hole diameter d1 (min) 1.5 hole position f ( 0.1) 11.5 compartment depth k (max) 2.85 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed
docid022886 rev 6 43/46 VND7012AY-E order codes 7 order codes table 17. device summary package order codes tube tape and reel powersso-36 VND7012AY-E vnd7012aytr-e
revision history VND7012AY-E 44/46 docid022886 rev 6 8 revision history table 18. document revision history date revision changes 05-mar-2012 1 initial release. 18-feb-2013 2 table 1: pin functions : ? gnd: updated functions definitions updated figure 2: configuration diagram (top view) 25-mar-2013 3 updated features list table 3: absolute maximum ratings : ?-i out , v esd : updated value ?i sense , e max : updated parameter and value updated table 4: thermal data table 5: power section : ?v clamp : added test conditions and value ?i stby , t d_stby , i l(off) : updated test conditions ?i gnd(on) : updated test conditions and value ?v f : added row updated table 6: switching (v cc =13v; -40c docid022886 rev 6 45/46 VND7012AY-E revision history 16-jan-2014 5 table 5: power section : ?v f : updated test conditions updated table 6: switching (v cc =13v; -40c VND7012AY-E 46/46 docid022886 rev 6 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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